View CY62512V_256546.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fax id: 1098
PRELIMINARY
Features
* 2.7V-3.6V operation * CMOS for optimum speed/power * Low active power (70 ns, LL version) -- 144 mW (max.) * Low standby power (70 ns, LL version) -- 54 W (max.) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options
CY62512V
64K x 8 Static RAM
er-down feature that reduces power consumption by more than 99% when deselected. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE 2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62512V is available in standard 32-pin TSOP type I package.
Functional Description
The CY62512V is a high-performance CMOS static RAM organized as 65,536 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE 1), an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. This device has an automatic pow-
Logic Block Diagram
A11 A9 A8 A13 WE CE2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Configurations
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
TSOP I Top View (not to scale)
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O1
ROW DECODER
I/O2
SENSE AMPS 256 x 256 x 8 ARRAY
I/O3 I/O4 I/O5
CE1 CE2 WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A9 A 10 A 11 A 12 A 13 A 14 A 15
62512V-1
Selection Guide
CY62512V-55 Maximum Access Time (ns) Maximum Operating Current Maximum CMOS Standby Current Com'l Ind'l
Shaded areas contain advance information.
CY62512V-70 70 40 mA 100 A 15 A 30 A
55 40 mA L LL LL 100 A 15 A 30 A
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 April 6, 1998
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage[1]..................................-0.5V to VCC +0.5V
CY62512V
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 2.7V-3.6V
Electrical Characteristics Over the Operating Range
62512V Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs GND VI VCC GND VI VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 VIH or CE2 < VIL, VIN VIH or VIN VIL, f = fMAX Max. VCC, CE1 VCC - 0.3V, or CE2 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f=0 L Com'l Ind LL LL Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1mA 2.0 -0.3 -1 -1 0.1 0.1 20 20 15 15 0.4 0.4 0.4 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 40 40 300 300 100 15 30 Typ.[3] Max. Unit V V V V A A mA mA A A A A A
ISB1
ISB2
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested. 4. Tested initially and after any design or process changes that may affect these parameters.
2
PRELIMINARY
Switching Characteristics[5] Over the Operating Range
62512V-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[7] OE HIGH to High Z
[6, 7] [7] [6, 7]
CY62512V
62512V-70 Min. 70 Max. Unit ns 70 10 70 35 10 25 10 25 0 70 70 60 60 0 0 55 30 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 ns
Description
Min. 55
Max.
55 10 55 25 10 20 10 20 0 55 55 45 45 0 0 40 25 0 5 20
CE1 LOW to Low Z, CE2 HIGH to Low Z
CE1 HIGH to High Z, CE2 LOW to High Z
CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down
[8]
Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z
[7]
WE LOW to High Z[6,7]
Shaded areas contain advance information. Note: 5. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
PRELIMINARY
Data Retention Characteristics (Over the Operating Range for "L" and "LL" version only)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current No input may exceed VCC + 0.3V VCC = VDR = 3.0V, Com'l LL CE > VCC - 0.3V, Ind'l LL VIN > VCC - 0.3V or VIN < 0.3V L Conditions Min. 2.0 0.4 0.4 0.4 0 tRC Typ.[3]
CY62512V
Max.
Unit V
80 12 25
A A A ns ns
tCDR[4] tR
Chip Deselect to Data Retention Time Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
62512-5
VDR > 2V
3.0V tR
Switching Waveforms
Read Cycle No.1[9,10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID
[10,11]
DATA VALID
62512V-6
Read Cycle No. 2 (OE Controlled)
ADDRESS
tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50%
62512V-7
HIGH IMPEDANCE
ICC ISB
Notes: 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[12,13]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
CY62512V
62512V-8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12,13]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 14 tHZOE
Note: 12. Data I/O is high impedance if OE = VIH. 13. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied.
tHD
DATAIN VALID
62512V-9
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[12,13]
tWC ADDRESS tSCE CE1
CY62512V
CE2 tSCE tAW tSA WE tSD DATAI/O NOTE 14 tHZWE DATA VALID tLZWE
62512V-10
tHA tPWE
tHD
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 70 Ordering Code CY62512VLL-70ZC Package Name Z32 Package Type 32-Lead Thin Small Outline Package Operating Range Commercial
Document #: 38-00640
6
PRELIMINARY
Package Diagram
CY62512V
32-Lead Thin Small Outline Package Z32
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY62512V

	To Download CY62512V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .